(VTS'19) 
April 23-25, 2019 
Monterey, CA (USA)   

The IEEE VLSI Test Symposium explores emerging trends and novel concepts in the testing of integrated circuits and systems. The symposium is a leading international forum where many of the world’s leading test experts and professionals from both industry and academia join to present and debate key issues in testing. 

VTS 2019 addresses key trends and challenges in the semiconductor design and manufacturing industries through an exciting program that includes Keynote and Plenary Talks, Technical Paper Sessions, Embedded Tutorials, Panels, Hot Topic Sessions, and the Innovative Practices Tracks.

The core of VTS 2019, the three day technical program, responds to the many trends and challenges in the semiconductor design and manufacturing industries, with papers and contributions covering a diverse and seminal set of topics including: Analog, Mixed-Signal & RF Test; 2.5 and 3D Test; Test ATPG & Compression; Delay and Performance Testing; Test Standards and Scan Test; Structural and Cell Aware Test, On-Line Test & Error Correction; Learning Based Diagnosis, Test and Security; Hardware Security.

In addition to the three-day paper sessions, VTS 2019 features several special sessions including one plenary, wine-and-cheese evening panel, one panel, four hot topic sessions, one embedded tutorial, two new topic sessions and two student activity sessions. 

VTS 2019 continues the tradition of featuring the Innovative Practices track. Sessions cover challenging topics including Automotive, Machine Learning and AI, Cybersecurity, In-field testing, etc. The sessions that make up this track highlight cutting-edge challenges faced by test practitioners, and innovative solutions employed to address them. 

The full program is available at: http://tttc-vts.org/public_html/new/2019/technical-program/

Full registration includes breakfasts, lunches, coffee breaks, social event, and electronic distribution of the symposium proceedings.

Student registration includes all of the above except the social event.

Discounted advance registration prices are valid until April 15, 2019. Cancellations are allowed until April 15, 2019 at an administrative fee of $75. Substitutions are allowed until April 20, 2019, at no cost. For either of the above or any other registration questions, please contact the registration chair, Ke Huang  <khuang@sdsu.edu>.

For general information:

General Chair:

• Chen-Huan Chiang - Intel Inc.

Program Co-Chairs:

• Stefano Di Carlo - Politecnico di Torino
• Peilin Song - IBM Research

Past Chair:

• Yiorgos Makris - University of Texas at Dallas

Vice-General Co-Chairs:

• Lorena Anghel - University of Grenoble-Alpes / TIMA Laboratory

Vice-Program Co-Chairs:

• Mehdi Tahoori - Karlsruhe Institute of Technology
• Sule Ozev - Arizona State University

Innovative Practices Track Co-Chairs:

• Peter Sarson - Dialog Semiconductor
• John Carulli - Globalfoundries

Special Sessions Co-Chairs:

• Jennifer Dworak - Southern Methodist University
• Maria Michael - University of Cyprus

Publications:

• Ioana Vatajelu (Chair) - TIMA Laboratory
• Giorgio Di Natale (Member) - LIRMM

Publicity Co-Chairs:

• Alessandro Savino - Politecnico di Torino

Steering committee

• M. Abadir – Abadir & Associates
• J. Figueras – Universidad Polytecnic de Catalunya
• A. Ivanov – University of British Columbia
• M. Nicolaidis – TIMA Laboratory
• P. Prinetto – Politecnico di Torino
• A. Singh – Auburn University
• P. Varma – Real Intent
• Y. Zorian – Synopsys

The IEEE VLSI TEST SYMPOSIUM is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).